DS1624S+T&R【PDF 3/18 页】IC THERM/EEPROM DIG 256BYT 8SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录39

1页 2页 [3页]4页 5页 6页 7页

DS1624

f 1

2-WIRE SERIAL DATA BUS

The DS1624 supports a bidirectional two-wire bus and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that

controls the message is called a master. The devices that are controlled by the master are slaves. The

bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,

and generates the START and STOP conditions. The DS1624 operates as a slave on the two-wire bus.

Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol

has been defined (see Figure 2):

" Data transfer may be initiated only when the bus is not busy.

" During data transfer, the data line must remain stable whenever the clock line is high. Changes in the

data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain high.

Start data transfer: A change in the state of the data line, from high to low, while the clock is high,

defines a START condition.

Stop data transfer: A change in the state of the data line, from low to high, while the clock line is high,

defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the high period of the clock signal. The data on the line must be changed

during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited, and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth bit.

Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate)

are defined. The DS1624 works in both modes.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse, which is associated with

this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable low during the high period of the acknowledge related

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an

end of data to the slave by not generating an acknowledge bit on the last byte that has been

clocked out of the slave. In this case, the slave must leave the data line high to enable the master

to generate the STOP condition.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式